This website is intended to be a showcase and collaboration platform supporting activities of Vertical Slit Transistors Integrated Circuits ( VeSTICs) Research Group.
It can be used as:
- An entry point for the active members of VeSTICs Research Group, called "Insiders",
- IP outlet for potential future Insiders and future customers, called "Cheerleaders"
- A showcase of the newest results constructed with the skeptical but competent opponents, as well as passive supporters, of the VeSTICs vision in mind. (We call them the "Majority").
can use the links in the left bar. Cheerleaders
can access more information available only after registration. Insiders
have access to everything. In addition, insiders
have the ability to add and modify content of this website.
To become a Cheerleader please register using link located in the top bar of this page.
A new 3D IC Integration Paradigm
VeSTICs introduces a new and true 3-dimensional IC integration paradigm. It is based upon a newly invented transistor (VeSFET) where the gate oxide is in a vertical plane. In fact there are two gates per transistor enclosing a channel (slit) for current to flow. The transistor is surrounded by four metal piilars tha serve as gate terminals (2) and one each for source and drain. A 3D picture of an inverter implemented in this topolgy is shown in Figure (c) on the right. Note that this transistor topology allows interconnect on the sides of the chip not only allowing more flexibility in layout but also higher density and utilization of silicon real-estate.
Figure (a) shows layout view of the inverter rendered in a traditional way. However with this view it is not easy to illustrate the connecting metal layers on both sides of the transistor (upper and lower). Figure (b) illustrates how the two transistors are connected on each side to form an inverter. Notice how most of the shapes are circular unlike traditional rectangular shapes of ICs with planar transistors.
We firmly believe that this new paradigm can result in higher densities, higher yield, lower cost of manuafcturing, higher testability, lower power consumption, and high degree of design flexibility. There are many more advantages that can be illustrated through examples. But perhaps you are first a bit sceptical as to the feasibility of such transistor topology. You are welcome to browse the website to find out more about the proposed technology, experimental and simulated results and the incredible flexibility in circuuit design that this paradigm affords. This website is still under construction and if you have a specific question or feedback please use the contact page in the interim.